STS

Wafer size
Manual wafer lock
Vacuum
Pumps are not included[1]
The STS Multiplex ASE ICP is an inductively coupled plasma etching system designed for deep silicon etching.
The STS Multiplex ASE ICP uses low and high frequency inductively coupled plasma. The ASE process operates by alternating between an etching cycle that removes silicon and a deposition cycle that deposits a protective polymer layer on sidewalls, repeating to produce anisotropic, high-aspect-ratio features.[1]
The STS Multiplex ASE ICP is used after photolithography to transfer patterns into silicon substrates. Upstream process steps include photoresist coating, exposure, and development. Downstream steps include resist stripping, cleaning, and inspection.
The system is typically employed in the fabrication of microelectromechanical systems, through-silicon vias, and other devices requiring deep, high-aspect-ratio silicon features.
The STS Multiplex ASE ICP is used for deep silicon trench etching of a single six-inch substrate.[1]
Documented failure modes, common issues, and field considerations.
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The following facts about the Multiplex ASE ICP Deep Silicon are absent from this record as of this revision. First-hand knowledge or a citation closes a gap; every submission is reviewed before publication.
No publicly documented production dates or lifecycle milestones (introduction, end of production, EOL) for the Multiplex ASE ICP Deep Silicon are on record.
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No publicly documented variants, configuration options, or revision breakpoints of the Multiplex ASE ICP Deep Silicon are on record.
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The process node or technology generation of the Multiplex ASE ICP Deep Silicon is not on record.
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Last updated Oct 11, 2026.
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